FIG. 1 illustrates a photolithography step involving a semiconductor wafer 2, having a light sensitive photo-resist 4 formed on it A mask 6 is positioned over the semiconductor wafer 2 and comprises a transparent plate 7 and opaque regions 8 on the underside of the plate 7 forming an image that is projected onto the photo-resist 4 during a photolithography step. The plate 7 is for example made of quartz, and the opaque regions 8 are formed for example of molybdenum silicide (MoSi). As represented in FIG. 1, light 10 is shone through the mask 6, and an image reducing lens 12 is used to make a reduction in the size of the image projected on the photo-resist 4, such that the dimensions of the image projected on the wafer are smaller than those of the mask. The mask layout is for example four times larger than the image formed on layer 4.
FIG. 2A illustrates in plan view the surface of the photo-resist 4. Dashed lines 202, 204 and 206 show mask pattern boundaries as reduced to correspond to the size of the projected patterns on the photo-resist 4, and solid lines 208, 210 and 212 show the actual patterns that are projected on the photo-resist layer 4, for example determined by simulation. The actual projected patterns are distorted with respect to the mask pattern edges. In particular, the rectangular regions are narrower, and tend to have curved corners or line end pull backs. This distortion results from some dispersion and interference on the light as it passes through the mask and through the optical arrangement between the mask and the wafer.
FIG. 2B illustrates, by dashed lines 214, 216 and 218, adjustments made to the boundaries of the mask patterns in order to result in more accurate patterns being formed on the wafer. The technique of adjusting the mask pattern boundaries in this way is known as optical proximity correction (OPC).
During OPC, a model for the transmission (amplitude and phase) of the light passing through the mask is used. The model for the transmission of light through the mask corresponds to the near-field amplitude and phase transmission just after the light has passed through the mask. The simulation of the image formed on the wafer takes into account other effects, such as the diffraction of the light and the aberrations introduced by the optical arrangement positioned between the mask and the wafer. A cut-off level is then applied to the simulated light intensities at the wafer level in order to determine the regions where the photo-resist will be developed.
As illustrated in FIG. 2B, the corrections to the patterns of the mask layout could comprise extending end regions to form “hammer heads”, and thereby correct the pull back on line ends of the projected image. Generally, narrow openings on the mask are also made wider, such that in the image that is formed they have the desired width. Furthermore, concave inner corners of the mask pattern can be corrected by repositioning the mask pattern boundaries towards the interior of the corners, as shown by the feature labelled 222 in FIG. 2B.
When approximating the light transmission through the mask, the Kirchhoff approximation can be used, according to which the electric field is assumed to have a constant value for all points of the mask within a region of the same polarity. This implies that the percentage of light transmitted through the mask at a mask pattern boundary is assumed to be in the form of a step, for example equal to 100% where the mask is transparent, falling to around 6% where the mask is opaque. The Kirchhoff approximation implies a “Thin Mask” approximation (TMA) according to which it is assumed that the opaque layer 8 of the mask is infinitely thin. In other words, whereas the opaque layer 8 has certain thickness, labelled e in FIG. 1, it is assumed that this thickness is negligible.
The Kirchhoff approximation is adequate for some technologies down to the CMOS 65 nm and even 45 nm technologies nodes having smallest feature sizes of 65 nm or 45 nm respectively. As the illumination light is at a wavelength of 193 nm, even with a four-times reduction system, the feature sizes of CMOS 32 nm technology and below are smaller than this wavelength. Therefore, the 3D mask effects that are ignored by the Kirchhoff or thin mask model are no longer negligible.
As an alternative to the Kirchhoff approximation, a Domain Decomposition Method (DDM) has been proposed. This technique involves calculating near-field transmission amplitude and phase for some edges of the mask layout, based on a rigorous EMF (electromagnetic field) simulation, to determine a more realistic model of the 3D mask effects, whilst avoiding performing the full rigorous EMF calculation over the entire layout.
As shown in FIG. 3, assuming that the opaque layer of a mask has facing edges 300 and 302, the DDM method involves determining a first near-field curve 304 corresponding to the near-field transmission across the first edge 300, and then a second near-field curve 306 corresponding to the near-field transmission across the second edge 302. The same curves are generated for phase, and these curves may then be applied to all the edges of the mask having corresponding orientations. Curves are also determined for the two edges perpendicular to edges 300 and 302, thereby taking into account the polarization of the incident light. For unpolarized light, the modulus of the transverse electric and magnetic components TE and TM are equal, whereas for polarized light, one component can have a stronger modulus than the other. The complex amplitudes of the near-fields generated from each edge of the mask layout are then summed in order to calculate the near-field across the whole mask.
A problem with the DDM method is that it is computationally very demanding both in terms of runtime and memory usage. Assuming that sufficient memory can be provided, for a reasonably large and complex mask design, it may take hundreds of hours to perform OPC based on this model of the mask transmission amplitude and phase, whereas a corresponding calculation based on the Kirchhoff model may take only a few hours to perform.
There is a technical problem in generating a mask layout sufficiently accurately to cope with new CMOS technologies, while greatly reducing the computation time and complexity when compared to the DDM method.